Physical Design Engineer Job at Acceler8 Talent, San Francisco, CA

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  • Acceler8 Talent
  • San Francisco, CA

Job Description

Get AI-powered advice on this job and more exclusive features. This range is provided by Acceler8 Talent. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range $225,000.00/yr - $270,000.00/yr Direct message the job poster from Acceler8 Talent. Recruiting the top AI Hardware Engineers in the world. Acceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT. With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive latency and low-level hardware control. Their scalable hardware enables faster model development and accessibility for researchers and startups. Founded by two previous leaders of a FAANG company, they are leading the charge as the compute platform for AGI, crafting comprehensive solutions from silicon to systems. They are actively looking for a Physical Design Engineer. Responsibilities: Drive their silicon and physical design methodology, ensuring scalability across various design levels. Take ownership of entire subsystems or subsets and/or chip-level physical design tasks, including floor-planning, placement, routing, timing closure, and verification. Lead reviews and progress reporting, focusing on key metrics to achieve silicon milestones like design freeze and tapeout. Collaborate closely with design, DFT, and other physical design stakeholders to deliver top-tier performance, power, and area results. Coordinate with design services partners and third-party vendors for block-level and chip-level. Requirements: Proven experience in guiding physical design from RTL to silicon for subsystems and/or top-level functions in ASICs and SOCs. Demonstrated expertise in floorplanning, place and route, clock tree insertion, timing analysis, physical verification, and electrical sign-off. Project experience collaborating with design, verification, and DFT teams to optimize designs for performance, power, and area. Experience working with third-party design services partners to take designs from initial floor plan to sign-off and tapeout is desirable. If interested in joining them please apply here or reach out to Jwhitcomb@acceler8talent.com . Seniority level Mid-Senior level Employment type Full-time Job function Design, Engineering, and Management Industries Software Development, Semiconductor Manufacturing, and Computer Hardware Manufacturing Referrals increase your chances of interviewing at Acceler8 Talent by 2x. Get notified about new Physical Design Engineer jobs in San Francisco Bay Area . #J-18808-Ljbffr Acceler8 Talent

Job Tags

Full time,

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